Did I miss something, or did Intel present an analyst briefing on thirty-two nanometers less than two weeks ago? Last night, Mark Bohr gave another briefing as part of this year’s Intel Developer Forum. This time the topic was their 22 nm platform. I know Intel have been touting ever faster yield ramps, but this is ridiculous.

Pardon my attempt at humor. No, Intel is not quite ready to release a 22 nm logic process. After all, we are still waiting for their 32 nm Westmere CPU although I doubt it will be much longer. My point is that you need to be paying attention if you don’t want to confuse the timing of real product introductions.

Intel is certainly doing its job managing the media to make sure they have the best chance to understand what’s going on. The media relations staff working closely with the company’s key technologists have developed a systematic approach to rolling out the information. As Mark Bohr reminded us on last night’s call, it was exactly two years ago at IDF that the 32 nm SRAM test wafer was announced. Managing the message must be a lot easier when your process development team is that good at scheduling.

One analyst asked if 15nm would be on time. Mark Bohr chuckled that 22nm was already old news just a few minutes into his presentation. I thought it was funny, too, because the 32 nm production wafer announcements were still warm.

Intel needs people to know that they are ramping volumes on their newest process, qualifying the next generation, and working on future technologies - all in parallel. That’s why Mark always takes time explaining the difference between the yield enhancement stage, qualification, and pathfinding. As of today, that equates to 32 nm, 22 nm, and 15 nm. But I wouldn’t be surprised if a few bloggers, press or even people inside big consulting companies get Intel’s technology development cycles wrong. Watch for news about Intel 22 nm SRAMs shipping soon.

Intel provided two plan view SEM micrographs of SRAM cells at the metal gate level - one for highest density and one for low voltage.  At a measly 0.092 μm2, the dense SRAM is the smallest reported. One of the analysts on the call asked if Intel was releasing any details about gate length or pitch. Mark Bohr’s response was that he loved the press so much, he wanted to keep that bit of information for their briefing which followed ours. As a blogger I feel some kinship with the press, and I felt like I should have access to such an important piece of information. But if I call myself an analyst, I should be able to figure it out from the information we were provided.

Looking at the SEM image, I calculate the dense SRAM cell dimensions to be 0.178 μm by 0.518 μm. The aspect ration of this cell is shorter and fatter than the cell Intel employed at 45 nm. Proportionally, this means the contacted gate pitch would be close to 90 nm. Scaling down the production 32 nm platform gate pitch of 112.5 nm by 0.7 should put it under 80 nm for the 22 nm generation. That means the 22 nm team isn’t quite finished with the SRAM layout. It would be quite a surprise if Intel’s relentless approach to scaling didn’t push the production-ready 22 nm ground rules into line with the 0.7X scaling trend.

There were a number of other benchmarks reported on the call that I will simply list as a reward for anyone with the endurance to read this far:

22 nm shuttle chips are more than just SRAM including mixed signal components like PLLs

Continuing with 193 nm immersion, several layers of double patterning will be added to the 32 nm flow

PMOS saturation currents continue to close the gap on NMOS

In today’s world, we are immersed in news about the rapid advance of technology - particularly when it comes to semiconductors. By any reasonable measure, the arrival or new technology nodes  is very frequent, but they cycle is two years not two weeks. And Intel keeps on beating Moore’s Drum to that cadence. 22 nm should arrive at the end of 2011. If Intel PR keeps their rhythm, I will be kept occupied with leading-edge CPU process announcements and never get back to discussing the SoC process as I promised last week.